1. Field of the Invention
The present invention relates to differential voltage line drivers, and more particularly to drivers that might see both high and low voltage differential input voltage signals (LVDS) in applications using a large range of power supply voltages.
2. Background Information
LVDS is a low voltage, low power, differential technology that has been well known in the art for a number of years. It is defined in the TIA/EIA-644 standard and is an improvement over the earlier emitter coupled (ECL) and RS 422/485 differential drivers that are also well known in the art. The improvements generally include lower power, lower differential voltage swings of about 350 mV offset at about 1.25 V. High speed operations of LVDS are surpassing the 655 Mbps of the standard as applications strive for higher and higher speeds.
FIG. 1 shows an example of a generic LVDS driver with a 3.5 mA current source being switched by an H or box switch 4 into a twisted pair cable or co-ax transmission line 6. The transmission line is terminated by a resistor R equal to the characteristic impedance of the transmission line to prevent reflections (ringing). A twisted pair cable typically has a characteristic impedance of about 100 ohm, so R would be about 100 ohms. Typical co-ax lines have impedances of 50 to 75 ohms and so R would be 50 or 75 ohms.
If the transistors are all N-type MOSFET's, and with point A high and B low, Q1 and Q4 are on and Q2 and Q3, respectively, are off. The 3.5 mA current 8 is directed through Q1, through the transmission line and the terminating resistor R and to ground through Q4 as shown. If R is 100 ohms there will be a +350 mV signal from point 10 to 12 across R and the inputs of a differential voltage receiver 14. When point B is high and A low, the current flows through Q2 and Q3, reverses through R creating a +350 mV signal from point 12 to 10. In FIG. 1, if Q2 and Q3 are on, point 10 will be about +1 volt and point 12 will be a +1.35 volts. A similar state will exist when Q4 is on where point 12 will be at +1 volt and point 10 at +1.35 volts. In short, there will be a common mode voltage at the inputs to the receiver 14 of about +1.175 volts (the 1 volt plus ½ of the 0.350 volts). In the example shown, the common mode voltage is at 1.175 V, but other levels can be designed as applications may require.
FIG. 1B illustrates a box switch but with the upper transistors being p-types MOSFET's. Similar operation in this circuit occurs except A1 and B1 signals drive devices on the same side of the box switch. When A1 is high and B1 low Q5 and Q7 are on and Q6 and Q8 are off. The circuits shown in FIGS. 1C, 1D operate in a similar fashion. FIG. 1C illustrates p-type transistors in all the box switch legs, and FIG. 1D illustrates the switch with bipolar NPN transistors. Similarly PNP transistors and combinations of NPN, PNP and even MOS transistors may be used. Other circuits with different active devices in various combinations will be known to those skilled in the art.
In FIG. 1A, if point A drives both Q2 and Q3 (similarly with B and Q1 and Q4) both on and off, the switching thresholds or the transistors and the supply voltage usually will force Q1 and Q2 to switch asymmetrically (that is not at the same input voltage level). For example, with B high and Q1 and Q4 on, the source of Q1 may be at about +1.350 V assuming there is a +1.0 V at the drain of Q4 and the 350 mA travels through an R of 100 ohms. In such a case, when point B drops, Q1 will switch off well before Q4 since the sources are at different voltage levels but they share the same gate signal. Moreover, if point A is being driven high as B is going low, Q3 will turn on before Q4 turns off and before Q2 turns on. In this state Q3 and Q4 will be on and Q1 and Q2 will be off. In such a case, both input ends of the transmission line 6 will be driven low at the same time resulting in waveform anomalies on the transmission line and a changing common mode level at the inputs to the receiver 14. Simply stated, in this example the common mode voltage at points 10 and 12 (the average of both points) will swing from 1 volts to 1.175 volts. This signal appears on both lines and may interfere with the proper receipt of the differential signal and will be a source of electromagnetic noise as described below.
Differential receiver circuits generally have very good common mode rejection ratios (CMRR). A low frequency common signal at both inputs 10 and 12 of a circuit with “good” CMRR will result in a small OUT signal compared to the OUT signal from a differential input. But, in the instance of a high frequency common mode signal, problems occur where the common mode signal may interfere with the receipt of the differential signals causing data errors, and may radiate EMI.
When the transmission line is a twisted pair carrying a differential signal, succeeding twists generate opposing electromagnetic fields that tend to cancel each other distal from the line itself. In contrast, however, a common mode signal appears on both conductors of a twisted pair and no canceling occurs. The net effect of the twist in a twisted pair is negated for common mode signal. Therefore, the electromagnetic interference generated by a common mode signal increases substantially at higher frequencies, and the industry is driving for higher and higher frequencies.
It would be advantageous to keep the common mode signal stable and unchanging.
One solution to this common mode problem is to have the switching of the driving transistors in the box circuit switch symmetrically—at the same time and at the same input voltage levels. Another approach would be to accommodate the different switching thresholds while providing means to minimize the negative effects.
Another problem occurs when the same line driver is used with high level signals and supply voltages (e.g. TTL circuits) and with LVDS signals and supply voltages. When the lower supply levels are used, there is a voltage loss through the stacked devices connecting the transmission line to the supply voltages. This reduces the available voltage drive to the line and reduces the available output voltage signal across the termination resistor. The reduced drive also reduces the frequency capability of the circuitry. This loss of capability is due, in part, to the reduced current available to drive the capacitances via the various on resistances of the devices involved. It would be advantageous to accommodate these various signal levels but minimize the negative effects.
U.S. Pat. No. 6,281,714 B1 ('715) is representative of the many patents in the general art of differential drivers. The '715 patent addresses some of the issues and problems discussed above. The '715 patent notices that at lower supply voltage, especially, the differential drivers necessarily slow down due to lack of drive current from the power supplies. This, of course, is magnified when the supply voltages are low and where thresholds, and series resistance drops in on MOSFET's, etc., limit the current available to charge capacitances during the signal transitions while driving the (low impedance) transmission line. The '715 addresses this slow down by supplying additional current drive through the box switch to the differential outputs, during the switching of the circuit from one state to another. The additional current is in parallel with the typical current source found in the prior art. The '715 patent however, by supplying current through the box switch transistors, still has limitations at low supply voltage levels due to “stacking” of the transistors—one above another wherein their voltage drops add and provide a low limit on the supply voltage.
LVDS circuits generally use +2.4 volt supply voltages and switch around +1 to about +1.4 volts. But often, LVDS drivers receive input signals generated from other logic families that use higher supply voltages and higher signal levels. For example, a TTL signal of 0 to +5V or 0 to +3.6V driving points A and B (obviously from true and not true sources) may drive a LVDS line driver.
It would be advantageous to receive signals from high level logic families, like TTL, together with signals from low logic level families, like LVDS and ECL (emitter coupled logic) and RS 422/485 circuits.
The present invention addresses problems in the prior art while providing advantages related to speed and the range of power supply voltages.